Accelerate your project

FPGA logical circuit design is
entering an era of assembling IP cores.

Quality & Speedy
High quality and short lead time will enhance
your earning power.

POINT
1

Timely product introduction will require drastic reduction in man-hours for FPGA design and test.

POINT
2

If your wanted function is already standardized, do not work on it, but just use an IP core to conform to the standard.

POINT
3

IP cores drastically reduce development man-hours, and moreover, they give solutions to the problems of reliability and interoperability.

Video over IP

We have been taking part in Video-over-IP related activities since ten years ago, and now video distribution services (Video on Demand) have become prospering since 2015. With such a wind at our back, we are committed to fully utilizing every experience for the development of IP cores in this field including the following:

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IP_SMPTE2022_TS

IP cores for TS over IP to conform to the SMPTE2022-1/2 standards
There are a transmitter and a receiver IP cores. A pair of them transports a multiple channel TS through a GbE or another circuit.

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IP_SMPTE2022_Video

IP cores for Video over IP to conform to the SMPTE2022-5/6 standards
There are a transmitter and a receiver IP cores. A pair of them transports multiple SD, HD, or 3G video signals through a 10GbE or another circuit.

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IP_SMPTE2059_Slave

IP core for a Salve to conform to the SMPTE2059 standard, which resolves the clock regeneration based on the SMPTE2022-6, SMPTE2110, NMI or other standard

Broadcast quality and never-freeze design

  • “Broadcast quality” brand we attained through a lot of development activities in collaboration with broadcast equipment manufacturers;
  • Never-freeze design technology to prevent broadcast accidents; Structure to return to the initial state always at the boundary between frames or others

High speed communication technology at a level high enough to carry out a national project

  • In the field of high speed communication, our technology is high enough not only to develop industrial-use routers but also to carry out the national project of OTN (Optical Transport Network) by us alone.

Record of zero-times remaking

  • No remaking has been required in the past 20 or more ASIC development projects we undertook.
  • In the field of FPGA development, we are using simulation techniques acquired through ASIC development and we are adopting the most up-to-date techniques such as the use of Lint and other tools.

Sticking to a beautiful RTL

  • Unified description style to care about every single space
  • Design style faithful to fundamentals like lining up TTL-ICs; “Simple is best.”

Training of backbone employees of a major semiconductor vendor

  • Gave lectures in the RTL design and logic composition courses (for two major semiconductor vendors)

“Simple is Best” is the basis of our design style.