Accelerate your project

FPGA logical circuit design is
entering an era of assembling IP cores.

Quality & Speedy
High quality and short lead time will enhance
your earning power.

POINT
1

Timely product introduction will require drastic reduction in man-hours for FPGA design and test.

POINT
2

If your wanted function is already standardized, do not work on it, but just use an IP core to conform to the standard.

POINT
3

IP cores drastically reduce development man-hours, and moreover, they give solutions to the problems of reliability and interoperability.

Video over IP

We have been taking part in Video-over-IP related activities since ten years ago, and now video distribution services (Video on Demand) have become prospering since 2015. With such a wind at our back, we are committed to fully utilizing every experience for the development of IP cores in this field including the following:

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IP_SMPTE2022

There are two types of IP cores for SMPTE 2022. For TS over IP is SMPTE 2022-1 / 2. For Video over IP is SMPTE 2022-5 / 6. The hitless of SMPTE 2022 - 7 corresponds to both.

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IP_SMPTE2110

IP_SMPTE 2110 is an IP core for video over IP conforming to the SMPTE 2110-10, 20, 30, and 40 standards. It transmits HD, 3G, 4K video of multiple channels on 10 GbE or 25 GbE line.

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IP_SMPTE2059

IP_SMPTE 2059 is an IP core for slaves compliant with SMPTE 2059-1 and 2 standards. Synchronize with the time of the Grand Master, and adjust the video clock and frame phase.

Broadcast quality and never-freeze design

  • “Broadcast quality” brand we attained through a lot of development activities in collaboration with broadcast equipment manufacturers;
  • Never-freeze design technology to prevent broadcast accidents; Structure to return to the initial state always at the boundary between frames or others

High speed communication technology at a level high enough to carry out a national project

  • In the field of high speed communication, our technology is high enough not only to develop industrial-use routers but also to carry out the national project of OTN (Optical Transport Network) by us alone.

Record of zero-times remaking

  • No remaking has been required in the past 20 or more ASIC development projects we undertook.
  • In the field of FPGA development, we are using simulation techniques acquired through ASIC development and we are adopting the most up-to-date techniques such as the use of Lint and other tools.

Sticking to a beautiful RTL

  • Unified description style to care about every single space
  • Design style faithful to fundamentals like lining up TTL-ICs; “Simple is best.”

Training of backbone employees of a major semiconductor vendor

  • Gave lectures in the RTL design and logic composition courses (for two major semiconductor vendors)

“Simple is Best” is the basis of our design style.